Package structure for a multi-chip integrated circuit
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United States of America Patent
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Issued Date -
Sep 23, 2004
app pub date -
Mar 20, 2003
filing date -
Mar 20, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2.sup.nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and the pin pad and being bonded with the bonding agent on the chip of the first chip.
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