Digital reactor protection system for preventing common-mode failures
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United States of America Patent
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Issued Date -
Jul 15, 2004
app pub date -
Nov 6, 2003
filing date -
May 7, 2001
priority date (Note) -
Abandoned
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Abstract
Disclosed is a digital reactor protction system capable of self-excluding a software common mode failure. The system comprises four channels, each channel includes two bistable processors, two local coincidence logic processors, two system interface processors, two initiation logics, two reactor trips, two engineered safety features actuation systems, two maintenance and test panels, and two operator modules; wherein one bistable processor and local coincidence processor provided in each channel include an A-type CPU and B-type operating system, respectively, and the other bistable processor and local coincidence processor provided in each channel includes a C-type CPU and D-type operating system, respectively; and wherein the A and C-type CPUs and the B and D-type operating systems are different form each other, respectively, and if a trip condition is produced at the 2of4 (2 out of 4) bistable processor, the local coincidence logic processor transfers a trip signal to the initiation logic to operate the reactor trip and a engineered safety features actuation system.
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