Single ended clock signal generator having a differential output
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United States of America Patent
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Dec 28, 2004
Grant Date -
Jun 24, 2004
app pub date -
Dec 20, 2002
filing date -
Dec 20, 2002
priority date (Note) -
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Abstract
Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.
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