High resolution 3-D circuit formation using selective or continuous catalytic painting
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United States of America Patent
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Issued Date -
May 13, 2004
app pub date -
Nov 12, 2002
filing date -
Nov 12, 2002
priority date (Note) -
Abandoned
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Abstract
A method of forming an electrical feature such as a 3-D circuit on a substrate is described. The method includes the following steps. A catalytic paint is first selectively deposited on the surface of a molded polymer substrate to form a paint coating of the substrate. A conductive metal such as copper or nickel is then deposited onto the coating to form a plating of the substrate. An electrical feature is then obtained by forming a precision conductive pattern in the conductive metal.
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