Method of manufacturing interconnection structure applied to semiconductor device
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United States of America Patent
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Issued Date -
May 6, 2004
app pub date -
Apr 4, 2003
filing date -
Oct 22, 2002
priority date (Note) -
Abandoned
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Abstract
A barrier metal layer constituted of a TiN layer and a Ti layer is formed on a surface of an interlayer insulating film and on an inside surface of an interconnection recess formed in the interlayer insulating film while a substrate is maintained at a temperature of at least 200.degree. C. and lower than 300.degree. C. The interconnection recess is filled with a conductive layer and an extra part of the conductive layer that is deposited on the interlayer insulating film is removed through such a polishing process to form a conductive plug. In the process of forming the barrier metal layer, as the substrate is maintained at the temperature, the residual stress in the deposited barrier metal layer can be reduced. Accordingly, it is achieved to suppress peeling which occurs at the interface between the barrier metal layer and the interlayer insulating film in the polishing process.
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