Fabrication method for solder bump pattern of rear section wafer package
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United States of America Patent
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Issued Date -
Apr 29, 2004
app pub date -
Mar 10, 2003
filing date -
Oct 23, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A fabrication method for solder bump pattern of rear section wafer package is disclosed and the method includes the steps of: (a) pattern-etching the wafer at a passivation layer for the positioning of the solder bump; (b) depositing the entire under bump metal layer, (c) performing an opening on a solder pad using a photoresistor of an appropriate thickness; (d) placing the wafer at a vacuuming system and a heating system, where at this instance, the solder is in a liquid state having a fluidity but without formation of bubbles; and (e) forming a solder bump pattern at the opening position of the photoresistor of under bump metal of the wafer.
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