Semiconductor device and manufacturing method thereof

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United States of America Patent

SERIAL NO

10374997

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Abstract

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A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTD6-6 MARUNOUCHI 1-CHOME CHIYODA-KU TOKYO 100-8280
HITACHI ULSI SYSTEMS CO LTDTOKYO
AKITA ELECTRONICS SYSTEMS CO LTD85 AZA USHIRONO AIKAWA YUWA-MACHI KAWABE-GUN AKITA 010-1231

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akiyama, Yukiharu Tokyo, JP 37 649
Anjoh, Ichiro Tokyo, JP 78 1689
Eguchi, Shuji Naka-gun, JP 50 872
Hasebe, Akio Tokyo, JP 104 1807
Kimoto, Ryosuke Tokyo, JP 33 507
Koyama, Hiroshi Tokyo, JP 165 1316
Kudaishi, Tomoaki Komoro-shi, JP 33 494
Miyazaki, Chuichi Tokyo, JP 61 673
Nagai, Akira Hitachi-shi, JP 155 1854
Nishi, Kunihiko Tokyo, JP 117 3008
Nishimura, Asao Tokyo, JP 156 3473
Ogino, Masahiko Hitachi-shi, JP 110 1695
Ohnishi, Takehiro Tokyo, JP 11 165
Shibamoto, Masnori Saitama-shi, JP 4 63
Shimada, Noriou Kawabe-gun, JP 11 91
Tanaka, Hideki Sagamihara-shi, JP 448 5293
Tsubosaki, Kunihiro Tokyo, JP 99 1825

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