Cache/prefetch frame of serial data system and operation method of the same
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United States of America Patent
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Issued Date -
Mar 18, 2004
app pub date -
Nov 29, 2002
filing date -
Sep 17, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A cache/prefetch frame of serial data system and an operation method of the same. The cache/prefetch frame has a main controller, a main controller bus, a prefetch circuit, and a serial memory. The cache/prefetch frame of serial data system uses a serial interface between the main controller and the serial memory, such that the pins of the interface are decreased and consequently, the cost is reduced. The low-cost prefetch circuit is built in the main controller to overcome the drawback of the relatively low bandwidth between the main controller and the serial memory. The operation method of the cache/prefetch frame uses clock control to determine the timing for providing a clock signal to the main controller, such that bugs or shutdown caused by long waiting time of the main controller is prevented.
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