Method and system for generating low density parity check codes

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United States of America Patent

APP PUB NO 20040019845A1
SERIAL NO

10353230

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An approach for generating a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting a certain part of the parity check matrix to be lower triangular, hence enabling a very simple encoding method that does not require the generator matrix of the code. The approach can also exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)). Additionally, an efficient decoding scheme is described where both bit nodes and check nodes are partitioned into groups. The edge values associated with each of the group can be placed together in memory simultaneously for bit nodes groups and check nodes groups. This architecture allows the multiple edges to be fetched from memory at a single clock cycle. A method of designing the parity check matrix that ensures the fetching of all the adjacent edges for a group of bit nodes or check nodes in a few clock cycles is described. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.

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Patent Owner(s)

Patent OwnerAddress
DTVG LICENSING INC2230 E IMPERIAL HIGHWAY EL SEGUNDO CA 90245

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eroz, Mustafa Germantown, MD 131 2936
Lee, Lin-Nan Potomac, MD 164 3818
Sun, Feng-Wen Germantown, MD 84 2591

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