Programmable single-chip device and related development environment
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United States of America Patent
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Issued Date -
Jan 22, 2004
app pub date -
Nov 25, 2002
filing date -
May 25, 2000
priority date (Note) -
Abandoned
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Abstract
A programmable single-chip device, comprising a programmable gate array (PGA) section, a DSP core and a RISC core. The device is ideal for prototyping and deploying low-to-moderate volume implementations of high-bandwidth algorithms, which have processing requirements split between front-end, high iteration, low-numeric-agility, 'wide' loadings, middle-end, moderate iteration, high-numerical-precision loadings and back-end, low-iteration, highly conditional loadings, without the commensurate problems inherent in the custom ASIC, joint FPGA/DSP/RISC (or even direct compilation to FPGA) solutions.
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