Apparatus and method for reducing interference between signal lines
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jan 22, 2004
app pub date -
Jul 19, 2002
filing date -
Jul 19, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
An integrated circuit including a first signal line disposed on a semiconductor substrate, a second signal line disposed on a first dielectric layer, the first dielectric layer disposed on the semiconductor substrate, a third signal line disposed on a second dielectric layer, the second dielectric layer disposed on the first dielectric layer, and at least two vias connecting the first signal line to the second signal line, wherein the second signal line does not span the region directly beneath the third signal line, and wherein at least a portion of the first signal line extends into the region directly beneath the third signal line.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully