Logarithmic mode CMOS image sensor with reduced in-pixel fixed

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20030234344A1
SERIAL NO

10217196

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A logarithmic mode CMOS image sensor capable of eliminating in-pixel fixed pattern noise. The image sensor includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a photodiode and a current source. The gate terminal of the first MOS transistor and the first connection terminal are tied at a first node point. The first node point is connected to a terminal with the highest voltage in the circuit. The gate terminal of the second MOS transistor and the second connection terminal of the first MOS transistor are tied at a second node point. The first connection terminal of the second MOS transistor is also connected to the terminal with the highest voltage. The gate terminal of the third MOS transistor is tied to a row select signal terminal and the first connection terminal of the third MOS transistor is tied to the second terminal of the second MOS transistor. The second connection terminal of the third MOS transistor is a voltage output terminal. The gate terminal of the fourth MOS transistor is tied to a control signal terminal and the first connection terminal of the fourth MOS transistor is tied to the second node point. The first connection terminal of the photodiode is tied to the second connection terminal of the fourth MOS transistor and the second connection terminal of the photodiode is tied to a ground terminal. The first connection terminal of the current source is tied to the second connection terminal of the third MOS transistor and the second connection terminal of the current source is tied to a ground terminal.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
TWIN HAN TECHNOLOGY CO LTD3F NO 179 YUNG-CHI ROAD TAIPEI R O C

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
King, Ya-Chin Chungli, TW 91 428
Lai, Liang-Wei Banchiau City, TW 3 5

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation