Method for making multi-chip packages and single chip packages simultaneously and structures from thereof
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United States of America Patent
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Issued Date -
Dec 4, 2003
app pub date -
May 29, 2002
filing date -
Apr 30, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for making multi-chip packages and single-chip packages simultaneously and structures thereof are provided. The method comprises the steps of chip-attaching, electrically connecting, encapsulating and electrically testing, all the step are executed on a package substrate with channel holes. The package substrate is selectively cut so as to form multi-chip packages and single-chip packages simultaneously. Each semiconductor package has a plurality of coplanar wiring substrates defined by the channel holes and selective cutting lines. A space between two adjacent wiring substrates is formed from corresponding channel hole and is filled with the isolating encapsulant so as to perform cushioning effect for reducing thermal stress and to improve the structure strength of the package assembly.
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