Method for stacking chips within a multichip module package
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United States of America Patent
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Issued Date -
Sep 25, 2003
app pub date -
Mar 20, 2002
filing date -
Mar 20, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for stacking chips within a multichip module package is disclosed. A first chip is bonded to a substrate. A passivation layer is then deposited on a top surface of the first chip. After a first adhesive layer has been deposited on top of the passivation layer, an interposer is placed on the adhesive layer. Next, a second adhesive layer is deposited on the interposer. Finally, a second chip is bonded to the interposer via the second adhesive layer.
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