Associative cache memory with replacement way information integrated into directory

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United States of America Patent

APP PUB NO 20030159003A1
SERIAL NO

10046056

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Abstract

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An associative cache memory having an integrated tag and LRU array storing pseudo-LRU information on a per way basis, obviating the need for a separate LRU array storing pseudo-LRU information on a per row basis. Each way of the integrated array stores decoded bits of pseudo-LRU information along with a tag. An encoder reads the decoded bits from all the ways of the selected row and encodes the decoded bits into standard pseudo-LRU form. The control logic selects a replacement way based on the encoded pseudo-LRU bits. The control logic then generates new decoded pseudo-LRU bits and updates only the replacement way of the selected row with the new decoded pseudo-LRU bits. Thus, the control logic individually updates only the decoded bits of the replacement way concurrent with the tag of the replacement way, without requiring update of the decoded bits in the non-replacement ways of the row.

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Patent Owner(s)

Patent OwnerAddress
IP FIRST L L C1045 MISSION COURT FREMONT CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gaskins, Darius D Austin, TX 97 1553
Hardage, James Austin, TX 1 16

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