Packet communication device, packet communication system, packet communication module, data processor, and data transfer system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
May 22, 2003
app pub date -
Nov 19, 2002
filing date -
Nov 20, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
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