Shallow trench isolation polishing using mixed abrasive slurries
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United States of America Patent
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Issued Date -
May 15, 2003
app pub date -
Mar 13, 2002
filing date -
Sep 13, 2001
priority date (Note) -
Abandoned
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Abstract
Isolation of active areas, e.g. transistors, in integrated circuits and the like so that functioning of one active area does not interfere with the neighboring ones, is provided by the shallow trench isolation technique followed by chemical-mechanical polishing with a mixed abrasive slurry consisting essentially of at least two inorganic metal oxide abrasive material particles at a pH below five, preferably on the order of 3.5 to 4.0, in order to control the polish rate selectivity of silicon dioxide to silicon nitride of the circuit and to reduce surface defects.
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