Method for fabricating semiconductor device
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United States of America Patent
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Issued Date -
May 8, 2003
app pub date -
Oct 29, 2002
filing date -
Nov 8, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for fabricating a semiconductor device in which a wiring having a thickness with a high uniformity can be formed in the process of wiring formation using a dual damascene technology. In the method, an insulating film being patterned is formed on a semiconductor wafer, followed by forming a Cu film on both a wiring formation area which the insulating film is not formed and said insulating film. Then, the Cu film is mechanically polished until a step caused by a wiring layout is disappeared. After that, the Cu film on the insulating film is polished using chemical and mechanical polishing procedures to form a wiring made of the Cu film in the wiring formation area.
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