Wafer level chip scale package and method of fabricating the same
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United States of America Patent
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Issued Date -
Apr 17, 2003
app pub date -
Dec 12, 2001
filing date -
Oct 17, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A wafer level chip scale package, having a chip, at least one dielectric layer, a stress buffer layer, multiple first solder balls and multiple second solder balls. By using an upper dielectric layer to cover a lower dielectric layer, the peeling effect between the dielectric layers is mitigated. Further, by forming the stress buffer layer and the chip with a stair-like structure, the peeling effect of the stress buffer layer is also mitigated, while the probability of moisture penetration into the package is minimized. A method for fabricating the above wafer level chip scale package is also introduced.
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