Apparatus and methods for stacking integrated circuit devices with interconnected stacking structure
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United States of America Patent
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Issued Date -
Apr 10, 2003
app pub date -
May 28, 2002
filing date -
May 25, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures with solder bumps are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that conductive traces, vias and solder bumps form a unique conductive path for signals, which are accessed individually. Additionally, the structural integrity of the chip stack module is enhanced through the use and position of the solder bumps.
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