Fault isolation of individual switch modules using robust switch architecture
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United States of America Patent
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Issued Date -
Apr 3, 2003
app pub date -
Jan 2, 2002
filing date -
May 11, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A robust nonblocking switch architecture is presented, in the first and final stages made of switch modules which have extra, unallocated, input and output ports beyond those necessary to render the switch architecture nonblocking. Each middle stage has an extra switch module, affording it spare unallocated ports as well. A method of isolating a fault is also presented, given the robust switching architecture. Operating on each stage one at a time, the switching architecture is reconnected so as to bypass either the input, the output, or both the input and the output ports of the switch module in such stage impacted in the faulted signal path. Such method allows the isolation of the faulty switch module, and can be done automatically, with either external apparatus, or integrated fault isolation equipment.
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