Technique for compiling computer code to reduce energy consumption while executing the code
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jan 16, 2003
app pub date -
Mar 1, 2002
filing date -
Jul 9, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The present invention provides a technique for reducing power consumption during execution of computer code including power-down instructions, while satisfying user-specified real-time constraints on a microprocessor. In one example embodiment, this is accomplished by identifying one or more potential locations in the computer code where the power-down instructions can be inserted. The identified potential locations are then analyzed to select the locations to insert the power-down instructions based on user-specified real-time constraints so that the inserted power-down instructions reduces power consumption without significantly increasing the execution time of the computer code.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully