Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Dec 19, 2002
app pub date -
May 4, 2001
filing date -
May 4, 2001
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
An apparatus and method in a pipelined microprocessor for selecting one of a plurality of branch target addresses cached in a branch target address cache (BTAC) within a line selected by an instruction cache fetch address. The invention enables support for speculatively branching to one of a plurality of branch instructions potentially cached in an instruction cache line selected by the fetch address. Each target address has cached with it in the BTAC an associated offset within the instruction cache line of the previously executed associated branch instruction as well as a valid bit and a prediction of whether the branch instruction will be taken or not taken. Control logic selects the first, valid, taken, and seen target address. The target address is 'seen' if the associated offset is greater than or equal to a corresponding portion of the least significant bits of the fetch address.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully