Method and structure for retarding high temperature agglomeration of silicides using alloys
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United States of America Patent
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app pub date -
Jun 11, 2002
filing date -
Mar 6, 2000
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Abstract
Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.
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