Low voltage differential signaling output buffer
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United States of America Patent
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N/A
Issued Date -
Oct 3, 2002
app pub date -
Jun 4, 2001
filing date -
Jun 2, 2000
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention relates to methods and apparatus that advantageously provide relatively high-frequency data communication and relatively low power consumption in a low voltage differential signaling (LVDS) output buffer or driver. The LVDS output buffer includes an output resistance selected to terminate reflections from mismatched loads. Advantageously, a portion of the resistance is isolated by an emitter to base junction from a load applied to output terminals of the LVDS output buffer. A remaining portion of the resistance can thereby be reduced, advantageously allowing a reduction in power loss and reducing an amount of voltage swing at output transistors of the LVDS output buffer.
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