Integration and hold phase detection
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 5, 2002
app pub date -
Jun 4, 2001
filing date -
Jun 2, 2000
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The invention relates to methods and apparatus that allow a comparison of phase between a clock signal and a serial bitstream. A phase detector integrates a portion of a transition between adjacent or consecutive bits of the serial bitstream in a relatively fixed window. Advantageously, the relatively fixed window permits operation at relatively high frequencies such as at OC-192 rates of SONET. The integration result contains an amount of time within the window spent in one logic state versus the other. The integration results are held until the logic levels of the integrated bits are ascertained. An indication of a logic level transition is used to relate the integration result to the timing of the transition within the integration window. Multiple bit transitions can be integrated, correlated to timing information, summed, and provided as an input to, for example, a voltage controlled oscillator in a phase-locked loop.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully