Importance

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Abstract

A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.

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First Claim