Method and system for extraction of parasitic interconnect impedance including inductance
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United States of America Patent
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Nov 4, 2003
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N/A
app pub date -
Jan 24, 2002
filing date -
Jul 9, 1999
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Abstract
A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.
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