Digital clock recovery system
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United States of America Patent
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N/A
Issued Date -
Jul 11, 2002
app pub date -
Jan 3, 2002
filing date -
Jan 10, 2001
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A digital clock recovery circuit. The digital clock recovery circuit uses a lumped delay line and a digital phase detector to form a recovered clock signal. The recovered clock signal is limited to one clock period of the delay line so as to prevent false locking.
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