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Abstract

A computer process for extracting logic gates and/or functional cells from a transistor netlist. The process comprises the steps of scanning the netlist for transistor blocks of p-type and n-type transistors, determining if the p-type transistors and the n-type transistors are complementary or non-complementary and identifying the logic gate for each of the complementary transistor blocks and/or the functional cell for each of the non-complementary blocks. A transistor block is a group of p-type transistors connected through their sources and drains between a power node and a common node, and a group n-type transistors connected through their sources and drains between a ground node and the common node. Complementarity may be determined by iteratively seeking the serial connections and the parallel connections for the p-type transistors and the n-type transistors, identifying the main p-type transistor branch and the main n-type transistor branch, and comparing the branches.

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First Claim