Clock generating circuit
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United States of America Patent
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N/A
Issued Date -
Mar 21, 2002
app pub date -
Feb 27, 2001
filing date -
Sep 19, 2000
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The clock generating circuit includes: an oscillator generating a reference clock signal; an EX-OR gate connected in a ring configuration; and first and second D latch circuits. The EX-OR gate inverts a clock signal to provide the inverted clock signal to the first D latch circuit when an activating signal is at H level. In this case, the clock signal is a clock signal having a clock cycle period of twice that of the reference clock signal. The EX-OR gate provides the clock signal direct to the first D latch circuit when the activating signal is set to L level. In this case, level transition of the clock signal is ceased. Hence, generation of a glitch in the clock signal is prevented from occurring.
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