High density interconnection test connector especially for verification of integrated circuits
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United States of America Patent
Stats
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Mar 1, 2005
Grant Date -
Oct 18, 2001
app pub date -
Dec 13, 2000
filing date -
Dec 13, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
This invention pertains to a high density interconnection test connector intended especially for verification of integrated circuits, including a plate supporting a multiplicity of conductive pins one of the ends of which forms a contact zone with the electronic circuit to be tested and the other end forms a contact zone with a connecting plate that has a connection means with the test equipment, with the conductive pins presenting a form that is capable of ensuring flexibility and including a longitudinal component, characterized in that the pins present a succession of at least three arc-shaped sections (4, 5, 6) in alternating directions extended on both sides by rectilinear segments that are mobile according to one degree of freedom in axial translation, with the pins being inserted in the front plates.

First Claim
Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
UPSYS PROBE TECHNOLOGY SAS A CORPORATION OF FRANCE | 283 BOULEVARD JOHN KENNEDY F-91100 CORBEIL ESSONNES |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
George, Isabelle | Paris, FR | 2 | 52 |
Jurine, Jean-Michel | Nainville, FR | 1 | 1 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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