Importance

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Abstract

An integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith improves the overall access time in page and provides faster cycle time for read operations. In a particular embodiment, the cache may be provided as static random access memory ('SRAM') and the non-volatile memory array provided as ferroelectric random access memory wherein on a read, the row is cached and the write back cycle is started allowing subsequent in page reads to occur very quickly. If in page accesses are sufficient the memory array precharge may be hidden and writes can occur utilizing write back or write through caching. In alternative embodiments, the non-volatile memory array may comprise electrically erasable read only memory ('EEPROM') or Flash memory in conjunction with an SRAM cache or a ferroelectric random access memory based cache which has symmetric read/write times and faster write times than either EEPROM or Flash memory.

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First Claim