Clock frequency limiter
Number of patents in Portfolio can not be more than 2000
United States of America
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Apr 1, 2025
Grant Date -
Sep 12, 2024
app pub date -
May 15, 2024
filing date -
May 15, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.
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