Signal receiving apparatus, clock and data recovery circuit and clock and data recovery method thereof

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12267076
APP PUB NO 20250070786A1
SERIAL NO

18238023

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Abstract

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The present disclosure discloses a clock and data recovery circuit. A sampling circuit performs burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate over-sampling results. A selection circuit determines neighboring two of the over-sampling results having opposite logic states in the burst mode to select data edge sampling results and data center sampling results interlaced with each other and having the same time period with input analog data signal from the over-sampling results accordingly to be output sampling results. A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. A phase adjusting circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.

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Patent Owner(s)

Patent OwnerAddress
REALTEK SEMICONDUCTOR CORPORATIONNO 2 INNOVATION RD II HSINCHU SCIENCE PARK HSINCHU 30076

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fang, Chia-Peng Hsinchu, TW 1 0
Gu, Li-Jun Suzhou, CN 7 90
Huang, Peng Suzhou, CN 142 378
Kuan, Chi-Kung Hsinchu, TW 25 193
Tang, Zhi-Yong Suzhou, CN 1 0

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