Differential amplifier, semiconductor device and offset cancellation method
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United States of America
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Apr 1, 2025
Grant Date -
May 11, 2023
app pub date -
Oct 13, 2022
filing date -
Oct 13, 2022
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Abstract
Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
RENESAS ELECTRONICS CORPORATION | TOKYO JAPAN |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kaneda, Yoshinobu | Tokyo, JP | 11 | 88 |
Mitani, Hidenori | Tokyo, JP | 34 | 446 |
Nakano, Masaya | Tokyo, JP | 16 | 157 |
Shimoi, Takahiro | Tokyo, JP | 3 | 0 |
Takeda, Koichi | Tokyo, JP | 102 | 1910 |
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