Self-aligned contacts

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12266571
APP PUB NO 20240030067A1
SERIAL NO

18374976

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Abstract

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A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bohr, Mark T Aloha, US 107 2782
Ghani, Tahir Portland, US 756 7842
Hwang, Jack Portland, US 38 780
Joshi, Subhash M Hillsboro, US 45 1221
Klaus, Jason W Portland, US 27 1225
Mackiewicz, Ryan Beaverton, US 13 456
Rahhal-Orabi, Nadia M Lake Oswego, US 25 525
Steigerwald, Joseph M Forest Grove, US 36 883

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