Enlarging contact area and process window for a contact via
Number of patents in Portfolio can not be more than 2000
United States of America
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Apr 1, 2025
Grant Date -
Mar 14, 2024
app pub date -
Nov 16, 2023
filing date -
Nov 16, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
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