Memory device having row driver circuits for reducing leakage currents during power off
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United States of America
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Apr 1, 2025
Grant Date -
May 23, 2024
app pub date -
Nov 23, 2022
filing date -
Nov 23, 2022
priority date (Note) -
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Abstract
Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.
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