Multi-die mapping matrix multiplication

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United States of America

PATENT NO 12265494
SERIAL NO

18450985

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Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.

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Patent Owner(s)

Patent OwnerAddress
KEPLER COMPUTING INCSAN FRANCISCO CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dokania, Rajeev Kumar Beaverton, US 215 1136
Manipatruni, Sasikanth Portland, US 400 3194
Mathuriya, Amrita Portland, US 239 1338
Samajdar, Ananda Hillsboro, US 2 3

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