Repackaging IC chip for fault identification

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12265119
APP PUB NO 20240036108A1
SERIAL NO

18192745

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Abstract

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A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chien-Yi Hsinchu, TW 17 67
Ku, Min-Feng Hsinchu, TW 14 31
Lin, Chia Hong Hsinchu County, TW 4 0
Lin, Yu-Ting Hsin-Chu, TW 197 1249
Liu, Kao-Chih Changhua County, TW 3 0

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