Method and apparatus for an ultra low power VLSI implementation of the 128-bit AES algorithm using a novel approach to the shiftrow transformation
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United States of America
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Mar 25, 2025
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Jun 6, 2024
app pub date -
Nov 30, 2023
filing date -
Nov 30, 2023
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Abstract
The present techniques may provide improved processing and functionality of performance of the 128-bit AES Algorithm, which may provide improved power consumption. For example, in an embodiment, an encryption and decryption apparatus may comprise memory storing a current state matrix of an encryption or decryption process and a plurality of multiplexers configured to receive from the memory current elements of the state matrix stored in the memory, perform a cyclic shift on the received elements of the state matrix, and transmit the shifted elements to the memory for storage as a new state matrix.
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