Compact frequency-locked loop architecture for digital clocking

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12261612
APP PUB NO 20240297654A1
SERIAL NO

18177445

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Abstract

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Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

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Patent Owner(s)

Patent OwnerAddress
QUALCOMM INCORPORATED5775 MOREHOUSE DRIVE SAN DIEGO CA 92121

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abcarius, John San Diego, US 3 3
Bhatta, Debesh San Diego, US 8 16
Ondris, Robert Martin San Diego, US 1 0
Weil, Andrew San Diego, US 17 56
Yin, Wenjing San Diego, US 15 53

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