Frequency locked loop circuit and clock signal generation method

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12261610
APP PUB NO 20240056086A1
SERIAL NO

18496908

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Abstract

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A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

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Patent Owner(s)

Patent OwnerAddress
NOVATEK MICROELECTRONICS CORP2F NO 13 INNOVATION ROAD I SCIENCE-BASED INDUSTRIAL PARK HSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Chin-Tung New Taipei, TW 6 1
Chen, Chih-Wen Hsinchu County, TW 60 240
Hsu, Hao-Che Kaohsiung, TW 20 98
Lin, Li-Wei Hsinchu, TW 36 168
Luo, Ren-Hong Hsinchu, TW 9 16
Wang, Yan-Ting Hsinchu County, TW 3 4

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