Enhanced gate driver
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United States of America
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Mar 25, 2025
Grant Date -
Apr 25, 2024
app pub date -
Oct 19, 2022
filing date -
Oct 19, 2022
priority date (Note) -
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Abstract
Circuitry and methods for an improved gate driver circuit for power converters. The improved gate driver circuit substantially reduces propagation delay and transition losses in the floating-gate side of the gate driver circuit. One embodiment includes an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of a switching device. The inverter includes a first NFET having a control gate configured to be coupled to the state transition signal, a second NFET having a control gate coupled to the output of a reference circuit, and a PFET having a control gate configured to be coupled to the state transition signal, wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET and the conduction channels of the first NFET, second NFET, and PFET are coupled in series.
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