Memory core characteristic screening method and system thereof

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12260930
APP PUB NO 20240212728A1
SERIAL NO

18145927

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Abstract

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A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

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Patent Owner(s)

Patent OwnerAddress
INTEGRATED SILICON SOLUTION INC1623 BUCKEYE DR MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bang, Jeong Ho Milpitas, US 33 195
Cho, Kwang Rae Milpitas, US 7 14
Lee, Hyeon Jae Milpitas, US 11 195
Lee, Wol Jin Milpitas, US 5 9
Ryoo, Ki Hyung Milpitas, US 3 13
Yoon, Sun Byeong Milpitas, US 6 0

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