Memory devices with backside boost capacitor and methods for forming the same
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United States of America
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Mar 25, 2025
Grant Date -
Aug 31, 2023
app pub date -
Jun 8, 2022
filing date -
Jun 8, 2022
priority date (Note) -
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Abstract
A device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.
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