Non-volatile memory device with parallel programming
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United States of America
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Mar 25, 2025
Grant Date -
Apr 6, 2023
app pub date -
Mar 14, 2022
filing date -
Mar 14, 2022
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Abstract
A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.
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