Memory device with additional write bit lines
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United States of America
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Mar 25, 2025
Grant Date -
Apr 20, 2023
app pub date -
Dec 15, 2022
filing date -
Dec 15, 2022
priority date (Note) -
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Abstract
A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.
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