Compiler for implementing gating functions for neural network configuration
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 25, 2025
Grant Date -
N/A
app pub date -
Jul 29, 2019
filing date -
Jul 29, 2019
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.
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International Classification(s)
- 2019 Application Filing Year
- G06N Class
- 15814 Applications Filed
- 9207 Patents Issued To-Date
- 58.23 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G06N Class
- 0 % this patent is cited more than
- < 1 Age
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